In principle, in a semiconductor device constituted by a CMOS circuit, a path between a power supply and a GND is interrupted unless there is no change in the status. Therefore, in general, power consumption of the semiconductor device constituted by the CMOS circuit is small.
However, with high integration of the semiconductor device in recent years, a size of an MOS transistor (which will be simply referred to as a “transistor” hereinafter) constituting the CMOS circuit is becoming smaller. Also, there occurs a problem that a sub-threshold characteristic of the transistor is deteriorated and a leakage current disadvantageously flows as the size of the transistor is reduced and a gate length of the same becomes shorter.
Such a leakage current becomes a problem particularly in the semiconductor device having a function to set the built-in circuit portion in the standby mode. Such a semiconductor device is set in the standby mode because the power is wastefully consumed when the leakage current flows regardless of the purpose of further reducing the power consumption.
On the other hand, there is an advantage that the threshold voltage lowers and the operating speed is increased when the size of the transistor is small. There is a demand to keep this advantage even if the purpose is prevention of the leakage current.
In view of the above-described problem, there has been proposed a technique that the circuit portion which demands a fast operating speed is constituted by a transistor with a low threshold voltage, a switch is arranged between the circuit portion and a power supply and the switch is turned off to interrupt the power supply path to the circuit portion when setting in the standby mode.
For example, Japanese patent application laid-open publication No. 48525/1985 discloses a technique that a transistor having a channel length longer than a channel length of a transistor constituting the circuit portion (therefore having a high threshold voltage) is connected as a switch between the circuit portion which is set in the standby mode and the power supply portion. Further, Japanese patent application laid-open publication No. 29834/1994 discloses a technique that a transistor having a high threshold voltage is connected as a switch between a circuit using a transistor with a low threshold voltage and a power supply line and the leakage current can be suppressed while constituting a high-speed circuit. Both of these techniques adopt a high-threshold voltage transistor having a good sub-threshold characteristic as the switch. The leakage current of the high-threshold voltage transistor is far smaller than the leakage current of the low-threshold transistor. Therefore, when the transistor with a high threshold voltage is used, supply of the power to the circuit portion which is in the standby mode is substantially interrupted.
Meanwhile, in this type of semiconductor device, in order to cope with an instantaneous power supply fluctuation in the circuit portion which is in the normal operating mode, a capacitance portion for electric charge supply is connected in parallel with the circuit portion. This capacitance portion is referred to as a decoupling capacitance or a bypass capacitor.
FIG. 1 shows an example of the conventional semiconductor device having both the switch and the decoupling capacitance mentioned above.
Referring to FIG. 1, a semiconductor device 400 has an on-chip power supply terminal 101 connected to an external power supply (not shown) and an on-chip GND terminal 102 connected to an external GND (not shown). Further, the semiconductor device 400 has a first circuit portion 111, a switch 113 and a second circuit portion 120.
The first circuit portion 111 is constituted by a transistor with a low threshold voltage. A decoupling capacitance 114 is connected to the first circuit portion 111 in parallel. The switch 113 consists of a pMOS transistor with a high threshold voltage, and is connected to a connector between the first circuit portion 111 and the decoupling capacitance 114.
The second circuit portion 120 is constituted by, e.g., a transistor with a high threshold voltage, constantly receives supply of power, and never enters the standby mode. The second circuit portion 120 includes a control circuit 121 used to control the switch 113. The control circuit 121 generates a control signal 123 and controls the switch 113. As described above, the switch 113 is a pMOS transistor, and the control signal 123 is supplied to a gate of this pMOS transistor. When the control signal 123 is on a low level, the switch 113 is turned on.
When the first circuit portion 111 enters the standby mode, the switch 113 is turned off, and supply of power to the first circuit portion 111 is stopped.
Meanwhile, in the prior art semiconductor device mentioned above, when the first circuit portion 111 returns from the standby mode and shifts to the regular operating mode, various problems occur. For example, as shown in FIG. 2, immediately after the first circuit portion 111 returns to the operating mode from the standby mode, a temporal sudden drop 150 in a potential at the on-chip power supply terminal 101 (first connection point 131) occurs. Such problems will now be described in detail.
As shown in FIG. 1, the first circuit portion 111 and the second circuit portion 120 generally hav certain degrees of parasitic capacitances 112 and 122, respectively. When the switch 113 is in the on state, the parasitic capacitances 112 and 122 are charged together with the decoupling capacitance 114.
Here, when the switch 113 is turned off, the electric charges stored in the parasitic capacitance 112 of the first circuit portion 111 and the decoupling capacitance 114 are consumed as a leakage current of the first circuit portion 111. On the other hand, the parasitic capacitance 122 of the second circuit portion 120 is still stored. As a result, immediately before turning on the switch 113, only the parasitic capacitance 122 of the second circuit portion 120 stores the electric charge. When the switch 113 is turned on in this state, the electric charge stored in the parasitic capacitance 122 is redistributed between the parasitic capacitances 112 and 122 and the decoupling capacitance 114 until the balanced state is obtained. As a result, the potential of the on-chip power supply terminal 101 (first connection point 131) temporarily suddenly drops as described above (as denoted by reference character 150 in FIG. 2).
Furthermore, when the potential of the on-chip power supply terminal 101 (first connection point 131) is lowered, a transient current tries to flow through the semiconductor device 400 from the external power supply. At this moment, a bonding wire, a printed wiring or the like interposed between the on-chip power supply terminal 101 and the external power supply functions as a parasitic inductance L, and has an impedance of jωL when the transient current flows. Since this impedance jωL is an obstacle of smooth supply of the electric charge from the external power supply to the on-chip power supply terminal 101, it takes some time until the potential of the on-chip power supply terminal 111 or the like is stabilized.
Moreover, since the parasitic inductance and the parasitic capacitance constitute one type of LCR circuit, they may possibly oscillate. This oscillation may possibly cause a problem that it becomes a power supply noise and provokes the malfunction of any other non-illustrated circuit included in the semiconductor device 400.
It is an object of the present invention to solve the above-described problems in the prior art semiconductor device and provide a semiconductor device which can suppress a power supply noise generated when returning from the standby mode.